The invention relates to ordering transactions in a computer system.
Computer systems generally include one or more Peripheral Component Interface (PCI) buses that provide a special communication protocol between peripheral components, such as video controllers and network interface cards, and the computer system's main memory. When system memory and the peripheral components (PCI devices) reside on different buses, a bridge is required to manage the flow of data transactions between the two buses. PCI bus architecture is defined by the PCI Local Bus Specification, Revision 2.1 ("PCI Spec 2.1"), published in June 1995, by the PCI Special Interest Group, Portland, Oreg., incorporated by reference. PCI-to-PCI bridge architecture is defined by the PCI-to-PCI Bridge Architecture Specification, Revision 1.0 ("PCI Bridge Spec 1.0"), published in April 1994, by the PCI Special Interests Group, incorporated by reference.
Under the PCI Spec 2.1 and PCI Bridge Spec 1.0 architectures, PCI bridges support two types of transactions: posted transactions (including all memory write cycles), which complete on the initiating bus before they complete on the target bus, and delayed transactions (including memory read requests and I/O and configuration read/write requests), which complete on the target bus before they complete on the initiating bus. According to the PCI Spec 2.1, PCI-to-PCI bridges must strongly favor posted write transactions when determining the order in which transactions are to be performed on the target bus. The PCI Spec 2.1 requires that, in order to prevent lock-up conditions, the computer system must allow posted write cycles to bypass earlier-initiated delayed request cycles and must prevent delayed request cycles from bypassing earlier-initiated posted write cycles.